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CY7C64215
enCoReTM III Full Speed USB Controller
1.0 Features
* Powerful Harvard Architecture Processor -- M8C Processor Speeds to 24 MHz -- Two 8x8 Multiply, 32-bit Accumulate -- 3.0 to 5.25V Operating Voltage -- USB Temperature Range: 0C to +70C * Advanced Peripherals (enCoReTM III Blocks) -- Analog enCoRe III Block Provides: * Up to 14-bit ADCs -- 4 Digital enCoRe III Blocks Provide: * 8-bit PWMs * Full-Duplex UART * Multiple SPI Masters or Slaves * Connectable to all GPIO Pins * Complex Peripherals by Combining Blocks * Full-Speed USB (12 Mbps) -- Four Unidirectional Endpoints -- One Bidirectional Control Endpoint -- USB 2.0 Compliant -- Dedicated 256 Byte Buffer -- No External Crystal Required * Flexible On-Chip Memory -- 16K Flash Program Storage 50,000 Erase/Write Cycles -- 1K SRAM Data Storage -- In-System Serial Programming (ISSP) -- Partial Flash Updates -- Flexible Protection Modes -- EEPROM Emulation in Flash Programmable Pin Configurations -- 25-mA Sink on all GPIO -- Pull-up, Pull-down, High- Z, Strong, or Open Drain Drive Modes on all GPIO -- Configurable Interrupt on all GPIO Precision, Programmable Clocking -- Internal 4% 24-/48-MHz Oscillator -- Internal Oscillator for Watchdog and Sleep -- 0.25% Accuracy for USB with no External Components Additional System Resources -- I2C Slave, Master, and Multi-Master to 400 kHz -- Watchdog and Sleep Timers -- User-Configurable Low Voltage Detection -- Integrated Supervisory Circuit -- On-Chip Precision Voltage Reference Complete Development Tools -- Free Development Software (PSoCTM Designer) -- Full-Featured, In-Circuit Emulator and Programmer -- Full Speed Emulation -- Complex Breakpoint Structure -- 128K Bytes Trace Memory
*
*
*
*
enCoRe III Core
Figure 1-1. enCoRe III Block Diagram Cypress Semiconductor Corporation Document 38-08036 Rev. *A * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised September 26, 2005
CY7C64215
2.0 Applications
for the Sleep timer and WDT. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the enCoRe III. In USB systems, the IMO will self-tune to 0.25% accuracy for USB communication. enCoRe III GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
* PC HID devices -- Mice (Optomechanical, Optical, Trackball) -- Keyboards -- Joysticks * Gaming -- Game Pads -- Console Keyboards * General Purpose -- Barcode Scanners -- POS Terminal -- Consumer Electronics -- Toys -- Remote Controls -- USB to Serial
3.2
The Digital System
The Digital System is composed of 4 digital enCoRe III blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references.
Port 7 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
3.0
enCoRe III Functional Overview
enCoRe III is based on the flexible PSoC architecture and is a full-featured, full-speed (12 Mbps) USB part. Configurable analog, digital, and interconnect circuitry enable a high level of integration in a host of consumer, and communication applications. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in both 28-pin SSOP and 56-pin QFN packages. The enCoRe III architecture, as illustrated in Figure 1-1, is comprised of four main areas: enCoRe III Core, Digital System, Analog System, and System Resources including a full-speed USB port. Configurable global busing allows all the device resources to be combined into a complete custom system. The enCoRe III CY7C64215 can have up to seven IO ports that connect to the global digital and analog interconnects, providing access to 4 digital blocks and 1 analog block.
Digital Clocks From Core
To System Bus
To Analog System
DIGITAL SYSTEM
Digital enCoRe III Block Array
Row Input Configuration 8 8
Row 0
DBB00 DBB01 DCB02
4 DCB03 4
8 8
Row Output Configuration
GIE[7:0] GIO[7:0]
GlobalDigital Interconnect
GOE[7:0] GOO[7:0]
3.1
enCoRe III Core
The enCoRe III Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with up to 20 vectors, to simplify programming of real-time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 16K of Flash for program storage, 1K of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. enCoRe III incorporates flexible internal clock generators, including a 24-MHz IMO (internal main oscillator) accurate to 8% over temperature and voltage. The 24-MHz IMO can also be doubled to 48 MHz for use by the digital system. A lowpower 32 kHz ILO (internal low-speed oscillator) is provided
Figure 3-1. Digital System Block Diagram Digital peripheral configurations include those listed below. * Full-Speed USB (12 Mbps) * PWMs (8-bit) * UART 8-bit with selectable parity * SPI master and slave * I2C slave and multi-master The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller.
3.3
The Analog System
The Analog System is composed of 1 configurable block, comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very
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flexible and can be customized to support specific application requirements. enCoRe III analog function supports the Analog-to-digital converters (up to 2, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Analog blocks are arranged in a column of three, which includes one CT (Continuous Time - AC B00 or AC B01) and two SC (Switched Capacitor - ASC10 and ASD20 or ASD11 and ASC21) blocks, as shown in Figure 3-2.
Al l IO (E xcep t P o r t 7) P 0[ 7] P 0 [6]
P 0[ 5] P 0[ 3] P 0[ 1] AGNDIn RefIn Analog Mux Bus
P 0 [4] P 0 [2] P 0 [0]
P 2 [6]
P 2[ 3]
P 2 [4] P 2 [2] P 2 [0]
P 2[ 1]
decimator, low voltage detection, and power-on reset. Brief statements describing the merits of each resource follow. * Full-Speed USB (12 Mbps) with 5 configurable endpoints and 256 bytes of RAM. No external components required except two series resistors. Wider than commercial temperature USB operation (-10C to +85C). * Two multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math as well as digital filters. * The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. * Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. * The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. * Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. * HAPI interface for a 8-bit bus width to accommodate data transfer with an external microcontroller or similar device.
3.5
A C I0[1:0] A C I1[1:0]
enCoRe III Device Characteristics
Ar r ay In p u t C o n fi g u r a ti o n
enCoRe III devices have 4 digital blocks and 6 analog blocks. The following table lists the resources available for specific enCoRe III device. Table 3-1. enCoRe III Device Characteristics
Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital IO Digital Rows SRAM Size 1K 1K Flash Size 16K 16K
B l o ck Ar r ay
A C B 00 A S C 10 A S D 20
A C B 01 A S D 11 AS C 21
Part Number
CY7C64215 up to -28PVXC 22
A na log R e fe re nc e
I n ter fa ce to D i g ital S ys tem RefHi R e f Lo AGN D R efer en c e G en e r ato r s A G N D In R ef I n B andg ap
1 1
4 4
22 48
2 2
2 2
6 6
CY7C64215 up to 50 -56LFXC
4.0
Getting Started
M8C In ter face (Ad d r es s B u s, D a ta B u s, E tc .)
Figure 3-2. Analog System Block Diagram 3.3.1 The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin in ports 0-5. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. It can be split into two sections for simultaneous dual-channel processing. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array.
The quickest path to understanding enCoRe III silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the enCoRe III integrated circuit and presents specific pin, register, and electrical specifications. enCoRe III is based on the architecture of the CY8C24794. For in-depth information, along with detailed programming information, reference the PSoCTM Mixed-Signal Array Technical Reference Manual. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest enCoRe III device data sheets on the web at http://www.cypress.com.
3.4
Additional System Resources
4.1
Development Kits
System Resources provide additional capability useful to complete systems. Additional resources include a multiplier, Document 38-08036 Rev. *A
Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store Page 3 of 26
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contains development kits, C compilers, and all accessories for enCoRe III development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click USB (Universal Serial Bus) to view a current list of available items.
5.1
5.1.1
PSoC Designer Software Subsystems
Device Editor
5.0
Development Tools
The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the enCoRe III blocks. Examples of user modules are ADCs, SPIM, UART, and PWMs. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. PSoC Designer sets up power-on initialization tables for selected enCoRe III block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of enCoRe III block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It's also possible to change the selected components and regenerate the framework. 5.1.2 Application Editor
PSoC Designer is a Microsoft(R) Windows(R)-based, integrated development environment for the enCoRe III. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Refer to the PSoC Designer Functional Flow diagram below.) PSoC Designer helps the customer to select an operating configuration for the enCoRe III, write application code that uses the enCoRe III, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family.
PSoCTM Designer
Graphical Designer Interface
Context Sensitive Help
Commands
In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports the enCoRe III family of devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the enCoRe III devices. The embedded, optimizing C compiler provides all the features of C tailored to the enCoRe III architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. 5.1.3 Debugger
Results
Im portable Design Database Device Database Application Database Project Database User M odules Library PSoC Configuration Sheet
PSoCTM Designer Core Engine
Manufacturing Information File
Em ulation Pod
In-Circuit Emulator
Device Programm er
The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the enCoRe III device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. 5.1.4 Online Help System
Figure 5-1. PSoC Designer Subsystems
The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, Document 38-08036 Rev. *A Page 4 of 26
CY7C64215
each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions.
5.2
5.2.1
Hardware Tools
In-Circuit Emulator
A low-cost, high-functionality ICE Cube is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and will operate with all enCoRe III devices.
DeviceEditor
User Module Selection Placement and Parameter -ization Source Code Generator
6.0
Designing with User Modules
The development process for the enCoRe III device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the enCoRe III architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called enCoRe III Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The User Module library contains 8 peripherals: ADCINC, PWM8, UART, SPIM, SPIS, LCD, I2CHW, I2CM and USBFS. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit the designer to establish the pulse width and duty cycle. User modules also provide tested software to cut development time. The user module application programming interface (API) provides high-level functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that can be adapted as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks Document 38-08036 Rev. *A
Generate Application
ApplicationEditor
Project Manager Source Code Editor Build Manager
Build All
Debugger
Interface to ICE Storage Inspector Event & Breakpoint Manager
Figure 6-1. User Module and Source Code Development Flows The next step is to write your main program, and any subroutines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. Page 5 of 26
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The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE CUBE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
Acronym
Description
ILO IMO IO IPOR LSb LVD MSb PC PLL POR PPOR PSoC PWM SC SRAM
internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator switched capacitor static random access memory
7.0
7.1
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym Description
AC ADC API CPU CT ECO
alternating current analog-to-digital converter application programming interface central processing unit continuous time external crystal oscillator
7.2
Units of Measure
EEPROM electrically erasable programmable read-only memory FSR GPIO GUI HBM ICE full scale range general purpose IO graphical user interface human body model in-circuit emulator
A units of measure table is located in the Electrical Specifications section. Table 11-1 on page 11 lists all the abbreviations used to measure the enCoRe III devices.
7.3
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal.
Document 38-08036 Rev. *A
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8.0 56-Pin Part Pinout
The CY7C64215 enCoRe III device is available in a 56-pin package which is listed and illustrated in the following table. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss and Vdd are not capable of Digital IO.
Table 8-1. 56-Pin Part Pinout (MLF*)
Type Pin No. Digital Analog 1 IO I, M 2 IO I, M 3 IO M 4 IO M 5 IO M 6 IO M 7 IO M 8 IO M 9 IO M 10 IO M 11 IO M 12 IO M 13 IO M 14 IO M 15 IO M 16 IO M 17 IO M 18 IO M 19 Power 20 USB 21 USB 22 Power 23 IO 24 IO 25 IO M 26 IO M 27 IO M 28 IO M 29 IO M 30 IO M 31 IO M 32 IO M 33 IO M 34 IO M 35 IO M 36 IO M 37 IO M 38 IO M 39 IO M
CY7C64215 56-Pin enCoRe III Device
Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss D+ DVdd P7[7] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P4[4] Description Direct switched capacitor block input. Direct switched capacitor block input.
I, M IO, M IO, M I, M I, I, I, I, M M M M
I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL), ISSP-SCLK. Ground connection.
15 16 17 18 19 20 21 22 23 24
I2C Serial Data (SDA), ISSP-SDATA.
Type Pin No. Digital Analog 44 IO M 45 IO I, M 46 IO I, M 47 IO I, M 48 IO I, M 49 Power 50 Power 51 IO I, M 52 IO IO, M
40 41 42 43
IO IO IO IO
M I, M I, M M
P4[6] P2[0] Direct switched capacitor block input. P2[2] Direct switched capacitor block input. P2[4] External Analog Ground (AGND) input.
53 54 55 56
IO IO IO IO
IO, M I, M M M
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. * The MLF package has a center pad that must be connected to ground (Vss).
Document 38-08036 Rev. *A
M, I2C SCL, M, I2C SDA, M, M, I2C SCL,
Supply voltage.
Name P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Vss P0[7] P0[5]
Description External Voltage Reference (VREF) input. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Ground connection. Analog column mux input, integration input #1. Analog column mux input and column output, integration input #2. P0[3] Analog column mux input and column output. P0[1] Analog column mux input. P2[7] P2[5]
Vdd P7[7] P7[0] M, I2C SDA, P1[0] M, P1[2] M, P1[4] M, P1[6]
P1[7] P1[5] P1[3] P1[1] Vss D+ D-
25 26 27 28
A, I, M, A, I, M, M, M, M, M, M, M, M, M, M, M, M, M,
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14
56 55 54 53 52 51 50 49 48 47 46 45 44 43
P2[5], M P2[7], M P0[1], A, P0[3], A, P0[5], A, P0[7], A, Vss Vdd P0[6], A, P0[4], A, P0[2], A, P0[0], A, P2[6], M P2[4], M
MLF
(Top View)
42 41 40 39 38 37 36 35 34 33 32 31 30 29
P2[2], P2[0], P4[6], P4[4], P4[2], P4[0], P3[6], P3[4], P3[2], P3[0], P5[6], P5[4], P5[2], P5[0],
A, I, M A, I, M M M M M M M M M M M M M
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CY7C64215
9.0 28-Pin Part Pinout
The CY7C64215 enCoRe III device is available in a 28-pin package which is listed and illustrated in the following table. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss and Vdd are not capable of Digital IO.
Table 9-1. 28-Pin Part Pinout (SSOP)
Type Pin No. Digital Analog Name Description 1 Power GND Ground connection 2 IO I, M P0[7] Analog column mux input, integration input #1. 3 IO IO,M P0[5] Analog column mux input and column output, integration input #2. 4 IO IO,M P0[3] Analog column mux input and column output. 5 IO I,M P0[1] Analog column mux input. 6 IO M P2[5] 7 IO M P2[3] Direct switched capacitor block input. 8 IO M P2[1] Direct switched capacitor block input. 9 IO M P1[7] I2C Serial Clock (SCL). 10 IO M P1[5] I2C Serial Data (SDA). 11 IO M P1[3] 12 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK. 13 Power GND Ground connection 14 USB D+ 15 USB D-] 16 Power Vdd Supply voltage. 17 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA. 18 IO M P1[2] 19 IO M P1[4] 20 IO M P1[6] 21 IO M P2[0] Direct switched capacitor block input. 22 IO M P2[2] Direct switched capacitor block input. 23 IO M P2[4] External Analog Ground (AGND) input. 24 IO M P0[0] Analog column mux input. 25 IO M P0[2] Analog column mux input and column output. 26 IO M P0[4] Analog column mux input and column output. 27 IO M P0[6] Analog column mux input. 28 Power Vdd] Supply voltage.
CY7C64215 28-Pin enCoRe III Device
Vss AI,P0[7] AIO,P0[5] AIO,P0[3] AI,P0[1] P2[5] AI,P2[3] AI,P2[1] I2C P1[7] SCL, I2CSDA,P1[5] P1[3] I2CSCL, P1[1] Vss D +
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SSOP
28 27 26 25 24 23 22 21 20 19 18 17 16 15
V dd P0[6],AI P0[4],AI P0[2],AI P0[0],AI P2[4] P2[2],AI P2[0],AI P1[6] P1[4] P1[2] P1[0],I2CSDA V dd D -
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. * The MLF package has a center pad that must be connected to ground (Vss).
10.0 Register Reference
10.1 Register Conventions
10.1.1 Abbreviations Used
10.2 Register Mapping Tables
The enCoRe III device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are Reserved and should not be accessed.
The register conventions specific to this section are listed in the following table.
Convention Description
R W L C #
Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Page 8 of 26
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CY7C64215
10.3 Register Map Bank 0 Table: User Space
Addr (0,Hex) Access Name Addr (0,Hex) Access 00 RW PMA0_DR 40 RW 01 RW PMA1_DR 41 RW 02 RW PMA2_DR 42 RW 03 RW PMA3_DR 43 RW 04 RW PMA4_DR 44 RW 05 RW PMA5_DR 45 RW 06 RW PMA6_DR 46 RW 07 RW PMA7_DR 47 RW 08 RW USB_SOF0 48 R 09 RW USB_SOF1 49 R 0A RW USB_CR0 4A RW 0B RW USBIO_CR0 4B # 0C USBIO_CR1 4C RW RW 0D 4D RW 0E EP1_CNT1 4E # RW 0F EP1_CNT 4F RW RW 10 EP2_CNT1 50 # RW 11 EP2_CNT 51 RW RW 12 EP3_CNT1 52 # RW 13 EP3_CNT 53 RW RW 14 EP4_CNT1 54 # RW 15 EP4_CNT 55 RW RW 16 EP0_CR 56 # RW 17 EP0_CNT 57 # RW 18 EP0_DR0 58 RW 19 EP0_DR1 59 RW 1A EP0_DR2 5A RW 1B EP0_DR3 5B RW 1C EP0_DR4 5C RW PRT7DR RW 1D EP0_DR5 5D RW PRT7IE RW 1E EP0_DR6 5E RW PRT7GS RW 1F EP0_DR7 5F RW PRT7DM2 RW 60 DBB00DR0 20 # AMX_IN RW 61 DBB00DR1 21 W AMUXCFG RW 62 DBB00DR2 22 RW 63 DBB00CR0 23 # ARF_CR RW 64 DBB01DR0 24 # CMP_CR0 # 65 DBB01DR1 25 W ASY_CR # 66 DBB01DR2 26 RW CMP_CR1 RW 67 DBB01CR0 27 # 68 DCB02DR0 28 # 69 DCB02DR1 29 W 6A DCB02DR2 2A RW 6B DCB02CR0 2B # 6C DCB03DR0 2C # TMP_DR0 RW 6D DCB03DR1 2D W TMP_DR1 RW 6E DCB03DR2 2E RW TMP_DR2 RW 6F DCB03CR0 2F # TMP_DR3 RW 30 70 ACB00CR3 RW 31 71 ACB00CR0 RW 32 72 ACB00CR1 RW 33 73 ACB00CR2 RW 34 74 ACB01CR3 RW 35 75 ACB01CR0 RW 36 76 ACB01CR1 RW 37 77 ACB01CR2 RW 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and should not be accessed. Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F ASD20CR0 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 MUL1_X A9 MUL1_Y AA MUL1_DH AB MUL1_DL ACC1_DR1 AC ACC1_DR0 AD ACC1_DR3 AE ACC1_DR2 AF B0 RDI0RI B1 RDI0SYN B2 RDI0IS B3 RDI0LT0 B4 RDI0LT1 B5 RDI0RO0 B6 RDI0RO1 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Access RW RW RW RW RW RW RW RW Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access
RW RW RW RW RW RW RW RW
CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2
RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW
W W R R RW RW RW RW RW RW RW RW RW RW RW
CPU_F
RL
DAC_D CPU_SCR1 CPU_SCR0
RW # #
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10.4 Register Map Bank 1 Table: Configuration Space
Addr Addr Access Name (1,Hex) (1,Hex) 00 40 PRT0DM0 RW PMA0_WA 01 41 PRT0DM1 RW PMA1_WA 02 42 PRT0IC0 RW PMA2_WA 03 43 PRT0IC1 RW PMA3_WA 04 44 PRT1DM0 RW PMA4_WA 05 45 PRT1DM1 RW PMA5_WA 06 46 PRT1IC0 RW PMA6_WA 07 47 PRT1IC1 RW PMA7_WA 08 48 PRT2DM0 RW 09 49 PRT2DM1 RW 0A 4A PRT2IC0 RW 0B 4B PRT2IC1 RW 0C 4C PRT3DM0 RW 0D 4D PRT3DM1 RW 0E 4E PRT3IC0 RW 0F 4F PRT3IC1 RW 10 50 PRT4DM0 RW PMA0_RA 11 51 PRT4DM1 RW PMA1_RA 12 52 PRT4IC0 RW PMA2_RA 13 53 PRT4IC1 RW PMA3_RA 14 54 PRT5DM0 RW PMA4_RA 15 55 PRT5DM1 RW PMA5_RA 16 56 PRT5IC0 PMA6_RA RW 17 57 PRT5IC1 PMA7_RA RW 18 58 19 59 1A 5A 1B 5B 1C 5C PRT7DM0 RW 1D 5D PRT7DM1 RW 1E 5E PRT7IC0 RW 1F 5F PRT7IC1 RW 20 60 DBB00FN CLK_CR0 RW 21 61 DBB00IN CLK_CR1 RW 22 62 DBB00OU ABF_CR0 RW 23 63 AMD_CR0 24 64 DBB01FN RW CMP_GO_EN 25 DBB01IN RW CMP_GO_EN1 65 26 66 DBB01OU RW AMD_CR1 27 67 ALT_CR0 28 68 DCB02FN RW 29 69 DCB02IN RW 2A 6A DCB02OU RW 2B 6B 2C 6C DCB03FN RW TMP_DR0 2D 6D DCB03IN RW TMP_DR1 2E 6E DCB03OU RW TMP_DR2 2F 6F TMP_DR3 30 70 ACB00CR3 31 71 ACB00CR0 32 72 ACB00CR1 33 73 ACB00CR2 34 74 ACB01CR3 35 75 ACB01CR0 36 76 ACB01CR1 37 77 ACB01CR2 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and should not be accessed. Name Access RW RW RW RW RW RW RW RW Addr (1,Hex) 80 ASC10CR0 81 ASC10CR1 82 ASC10CR2 83 ASC10CR3 84 ASD11CR0 85 ASD11CR1 86 ASD11CR2 87 ASD11CR3 88 89 8A 8B 8C 8D 8E 8F 90 91 ASD20CR1 92 ASD20CR2 93 ASD20CR3 94 ASC21CR0 95 ASC21CR1 96 ASC21CR2 97 ASC21CR3 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 RDI0RI B1 RDI0SYN B2 RDI0IS B3 RDI0LT0 B4 RDI0LT1 B5 RDI0RO0 B6 RDI0RO1 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Name Access RW RW RW RW RW RW RW RW Name USBIO_CR2 USB_CR1 Addr Access (1,Hex) C0 RW C1 #
EP1_CR0 EP2_CR0 EP3_CR0 EP4_CR0
RW RW RW RW RW RW RW RW
RW RW RW RW RW RW RW
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU
MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP
RW RW RW RW RW RW RW RW
RW RW RW RW RW RW RW RW RW RW RW RW
IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5
RW RW RW RW RW RW RW CPU_F
DAC_CR CPU_SCR1 CPU_SCR0
C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
# # # #
RW RW RW RW
RW RW RW RW RW RW RW RW RW RW RW R
W W RW W RW RW
RL
RW # #
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CY7C64215
11.0 Electrical Specifications
This section presents the DC and AC electrical specifications of the CY7C64215 enCoRe III. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com. Specifications are valid for 0C < TA < 70C and TJ < 100C, except where noted. Specifications for devices running at greater than 12 MHz are valid for 0C < TA < 70C and TJ < 82C.
5.25
4.75 Vdd Voltage
lid ng Va at i er ion Op Reg
3.00
93 kHz CPU Frequency
12 MHz
24 MHz
Figure 11-1. Voltage versus CPU Frequency
The following table lists the units of measure that are used in this section.
Table 11-1. Units of Measure Symbol C dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol W mA ms mV nA ns nV W pA pF pp ppm ps sps s V Unit of Measure microwatts milliampere millisecond millivolts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts
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11.1 Absolute Maximum Ratings
Min. -55 Typ. - Unit Notes C Higher storage temperatures will reduce data retention time. +85 C +6.0 V Vdd + 0.5 V Vdd + 0.5 V +50 mA +50 mA Max. +100
Table 11-2. Absolute Maximum Ratings Parameter Description TSTG Storage Temperature
TA Vdd VIO VIO2 IMIO IMAIO ESD LU
Ambient Temperature with Power Applied -40 Supply Voltage on Vdd Relative to Vss -0.5 DC Input Voltage Vss - 0.5 DC Voltage Applied to Tri-state Vss - 0.5 Maximum Current into any Port Pin -25 Maximum Current into any Port Pin -50 Configured as Analog Driver Electro Static Discharge Voltage 2000 Latch-up Current -
- - - - - - - -
- 200
V mA
Human Body Model ESD.
11.2
Operating Temperature
Min. 0 0 Typ. - - Max. +70 +88 Unit C C Notes
Table 11-3. Operating Temperature Parameter Description TA Ambient Temperature TJ Junction Temperature
The temperature rise from ambient to junction is package specific. See "Thermal Impedance" on page 24. The user must limit the power consumption to comply with this requirement.
11.3
11.3.1
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-4. DC Chip-Level Specifications Parameter Description Vdd Supply Voltage Min. Typ. Max. Unit Notes 3.0 - 5.25 V See DC POR and LVD specifications, Table 11-12 on page 16. - 14 27 mA Conditions are Vdd = 5.0V, TA = 25C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. - 8 14 mA Conditions are Vdd = 3.3V, TA = 25C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, analog power = off. - 3 6.5 A Conditions are with internal slow speed oscillator, Vdd = 3.3V, 0C < TA < 55C, analog power = off. - 4 25 A Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55C < TA < 70C, analog power = off.
IDD5
Supply Current, IMO = 24 MHz (5V)
IDD3
Supply Current, IMO = 24 MHz (3.3V)
ISB
Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.[1] Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.[1]
ISBH
Note: 1. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions enabled.
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CY7C64215
11.3.2 DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-5. DC GPIO Specifications Parameter Description RPU Pull-Up Resistor RPD Pull-Down Resistor VOH High Output Level Min. Typ. 4 5.6 4 5.6 Vdd - 1.0 - Max. Unit Notes 8 k 8 k - V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. 0.8 V Vdd = 3.0 to 5.25. V Vdd = 3.0 to 5.25. - mV - nA Gross tested to 1 A. 10 pF Package and pin dependent. Temp = 25C. 10 pF Package and pin dependent. Temp = 25C.
VOL
Low Output Level
-
-
VIL VIH VH IIL CIN COUT
11.3.3
Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output
DC Full-Speed USB Specifications
- 2.1 - - - -
- - 60 1 3.5 3.5
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-6. DC Full-Speed (12 Mbps) USB Specifications Parameter Description USB Interface VDI Differential Input Sensitivity VCM Differential Input Common Mode Range VSE Single Ended Receiver Threshold CIN Transceiver Capacitance IIO High-Z State Data Line Leakage REXT External USB Series Resistor VUOH Static Output High, Driven Min. Typ. Max. Unit Notes
0.2 0.8 0.8 - -10 23 2.8 2.7 - 28 1.3
- - - - - - - - - - -
- 2.5 2.0 20 10 25 3.6 3.6 0.3 44 2.0
V V V pF A W V V V W V
| (D+) - (D-) |
VUOHI VUOL ZO VCRS
Static Output High, Idle Static Output Low USB Driver Output Impedance D+/D- Crossover Voltage
0V < VIN < 3.3V. In series with each USB pin. 15 k 5% to Ground. Internal pull-up enabled. 15 k 5% to Ground. Internal pull-up enabled. 15 k 5% to Ground. Internal pull-up enabled. Including REXT Resistor.
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11.3.4 DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-7. 5V DC Analog Output Buffer Specifications Parameter VOSOB TCVOSOB VCMOB ROUTOB Description Min. Typ. Max. Unit Notes Input Offset Voltage (Absolute Value) - 3 12 mV Average Input Offset Voltage Drift - +6 - V/C Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V Output Resistance Power = Low - 0.6 - W Power = High - 0.6 - W VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low 0.5 x Vdd + 1.1 - - V Power = High 0.5 x Vdd + 1.1 - - V VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low - - 0.5 x Vdd - 1.3 V Power = High - - 0.5 x Vdd - 1.3 V ISOB Supply Current Including Bias Cell (No Load) Power = Low - 1.1 5.1 mA Power = High - 2.6 8.8 mA PSRROB Supply Voltage Rejection Ratio 53 64 - dB (0.5 x Vdd - 1.3) < VOUT < (Vdd - 2.3). Table 11-8. 3.3V DC Analog Output Buffer Specifications Description Min. Typ. Max. Unit Notes Input Offset Voltage (Absolute Value) - 3 12 mV Average Input Offset Voltage Drift - +6 - V/C Common-Mode Input Voltage Range 0.5 Vdd - 1.0 V Output Resistance Power = Low - 1 - W Power = High - 1 - W VOHIGHOB High Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low 0.5 x Vdd + 1.0 - - V Power = High 0.5 x Vdd + 1.0 - - V VOLOWOB Low Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low - - 0.5 x Vdd - 1.0 V Power = High - - 0.5 x Vdd - 1.0 V ISOB Supply Current Including Bias Cell (No Load) Power = Low 0.8 2.0 mA Power = High 2.0 4.3 mA - PSRROB Supply Voltage Rejection Ratio 34 64 - dB (0.5 x Vdd - 1.0) < VOUT < (0.5 x Vdd + 0.9). Parameter VOSOB TCVOSOB VCMOB ROUTOB
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11.3.5 DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-9. 5V DC Analog Reference Specifications Parameter BG - - - - - - Description Bandgap Voltage Reference AGND = Vdd/2[2] AGND = 2 x BandGap[2] AGND = P2[4] (P2[4] = Vdd/2)[2] AGND = BandGap[2] AGND = 1.6 x BandGap[2] AGND Block to Block Variation (AGND = Vdd/2)[2] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Min. 1.28 Vdd/2 - 0.04 2 x BG - 0.048 P2[4] - 0.011 BG - 0.009 1.6 x BG - 0.022 -0.034 Typ. 1.30 Vdd/2 - 0.01 2 x BG - 0.030 P2[4] BG + 0.008 1.6 x BG - 0.010 0.000 Max. 1.32 Vdd/2 + 0.007 2 x BG + 0.024 P2[4] + 0.011 BG + 0.016 1.6 x BG + 0.018 0.034 Unit V V V V V V V
- - - - - - - - - - -
Vdd/2 + BG - 0.10 Vdd/2 + BG Vdd/2 + BG + 0.10 3 x BG - 0.06 3 x BG 3 x BG + 0.06 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077 P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6]+ 0.100 3.2 x BG - 0.112 Vdd/2 - BG - 0.04 BG - 0.06 2 x BG - P2[6] - 0.084 P2[4] - BG - 0.056 P2[4] - P2[6] - 0.057 3.2 x BG 3.2 x BG + 0.076 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.04 BG BG + 0.06 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134 P2[4] - BG + 0.026 P2[4] - BG + 0.107 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110
V V V V V V V V V V V
Table 11-10. 3.3V DC Analog Reference Specifications Parameter BG - - - - - - Description Bandgap Voltage Reference AGND = Vdd/2[2] AGND = 2 x BandGap[2] AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap[2] AGND = 1.6 x BandGap[2] AGND Column to Column Variation (AGND = Vdd/2)[2] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Min. 1.28 Vdd/2 - 0.03 Typ. 1.30 Vdd/2 - 0.01 Not Allowed P2[4] + 0.001 BG + 0.005 1.6 x BG - 0.010 0.000 Max. 1.32 Vdd/2 + 0.005 Unit V V
P2[4] - 0.008 BG - 0.009 1.6 x BG - 0.027 -0.034
P2[4] + 0.009 BG + 0.015 1.6 x BG + 0.018 0.034
V V V V
- - - - - - - - - - -
Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] - P2[6] - 0.048 P2[4] - P2[6] + 0.022 P2[4] - P2[6] + 0.092
V
V
Note: 2. AGND tolerance includes the offsets of the local buffer in the enCoRe III block. Bandgap voltage is 1.3V 0.02V.
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11.3.6 DC Analog enCoRe III Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-11. DC Analog enCoRe III Block Specifications Parameter Description RCT Resistor Unit Value (Continuous Time) CSC Capacitor Unit Value (Switched Capacitor) 11.3.7 DC POR and LVD Specifications Min. - - Typ. 12.2 80 Max. - - Unit k fF Notes
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical Reference Manual for more information on the VLT_CR register. Table 11-12. DC POR and LVD Specifications Parameter Description Min. Typ. Max. Unit Notes
VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7
Vdd Value for PPOR Trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b
-
2.91 4.39 4.55 2.82 4.39 4.55 92 0 0 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81
-
V V V V V V mV mV mV V V V V V V V V
-
-
- - - 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72
- - - 2.98[3] 3.08 3.20 4.08 4.57 4.74[4] 4.82 4.91
Notes: 3. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 4. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
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11.3.8 DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-13. DC Programming Specifications Parameter Description Min. Typ. Max. Unit Notes IDDP Supply Current During Programming or - 15 30 mA Verify VILP Input Low Voltage During Programming or - - 0.8 V Verify VIHP Input High Voltage During Programming or 2.1 - - V Verify IILP Input Current when Applying Vilp to P1[0] - - 0.2 mA Driving internal pull-down resistor. or P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] - - 1.5 mA Driving internal pull-down resistor. or P1[1] During Programming or Verify VOLV Output Low Voltage During Programming - - Vss + 0.75 V or Verify VOHV Output High Voltage During Programming Vdd - 1.0 - Vdd V or Verify FlashENPB Flash Endurance (per block) 50,000 - - - Erase/write cycles per block. FlashENT Flash Endurance (total)[5] 1,800,000 - - - Erase/write cycles. FlashDR Flash Data Retention 10 - - Years
Note: 5. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
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11.4
11.4.1
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-14. AC Chip-Level Specifications Parameter Description FIMO245V Internal Main Oscillator Frequency for 24 MHz (5V) FIMO243V Internal Main Oscillator Frequency for 24 MHz (3.3V) FIMOUSB Internal Main Oscillator Frequency with USB Frequency locking enabled and USB traffic present. FCPU1 CPU Frequency (5V Nominal) FCPU2 CPU Frequency (3.3V Nominal) FBLK5 Digital PSoC Block Frequency (5V Nominal) Min. 23.04 Typ. 24 Max. 24.96[6, 7] Unit Notes MHz Trimmed for 5V operation using factory trim values. MHz Trimmed for 3.3V operation using factory trim values. MHz 0C < TA < 70C
22.08 23.94
24 24
25.92[6,8] 24.06[7]
0.93 0.93 0 0 15 - - 46.08 - - 0
FBLK3 F32K1 Jitter32k Step24M Fout48M
Digital PSoC Block Frequency (3.3V Nominal) Internal Low Speed Oscillator Frequency 32-kHz Period Jitter 24-MHz Trim Step Size 48-MHz Output Frequency
Jitter24M1 24-MHz Period Jitter (IMO) Peak-to-Peak FMAX Maximum frequency of signal on row input or row output. TRAMP Supply Ramp Time
24.96[6,7] MHz 12.96[7, 8] MHz 49.92[6, 7, 9] MHz Refer to the AC Digital Block Specifications. 24 25.92[7, 9] MHz 32 64 kHz 100 ns 50 - kHz 48.0 49.92[6, 8] MHz Trimmed. Utilizing factory trim values. 300 ps - 12.96 MHz 24 12 48 - -
s
Notes: 6. 4.75V < Vdd < 5.25V. 7. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 8. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. 9. See the individual user module data sheets for information on maximum frequencies for user modules.
Jitter24M1
F24M
Figure 11-2. 24 MHz Period Jitter (IMO) Timing Diagram
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11.4.2 AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-15. AC GPIO Specifications Parameter FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min. 0 3 2 10 10 Typ. - - - 27 22 Max. 12 18 18 - - Unit MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10%-90% Vdd = 4.5 to 5.25V, 10%-90% Vdd = 3 to 5.25V, 10%-90% Vdd = 3 to 5.25V, 10%-90%
90% GPIO Pin Output Voltage 10%
TRiseF TRiseS
TFallF TFallS
Figure 11-3. GPIO Timing Diagram 11.4.3 AC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-16. AC Full-Speed (12 Mbps) USB Specifications Parameter TRFS TFSS TRFMFS TDRATEFS Description Transition Rise Time Transition Fall Time Rise/Fall Time Matching: (TR/TF) Full-Speed Data Rate Min. 4 4 90 12 - 0.25% Typ. - - - 12 Max. 20 20 111 12 + 0.25% Unit Notes ns For 50 pF load. ns For 50 pF load. % For 50 pF load. Mbps
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11.4.4 AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-17. AC Digital Block Specifications Function Description Min. Typ. Max. Unit Notes
Timer
Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture
50[10] - - 50[10] - - 20 50[10] 50[10] - -
- - - - - - - - - - -
- 49.92 25.92 - 49.92 25.92 - - - 49.92 49.92
ns MHz MHz ns MHz MHz ns ns ns MHz MHz 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V.
Counter
Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input
Dead Band
Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency
CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency
-
-
24.6
MHz
- - 50[10] - -
- - - - -
8.2 4.1 - 24.6 24.6
MHz MHz ns MHz MHz
Maximum data rate at 4.1 MHz due to 2 x over clocking.
Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking.
Note: 10. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
11.4.5
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-18. AC External Clock Specifications Parameter Description Min. Typ. Max. Unit Notes
FOSCEXT - -
Frequency for USB Applications Duty Cycle Power up to IMO Switch
23.94 47 150
24 50 -
24.06 53 -
MHz %
s
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11.4.6 AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-19. 5V AC Analog Output Buffer Specifications Parameter Description TROB Rising Settling Time to 0.1%, 1V Step, 100-pF Load Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100-pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100-pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100-pF Load Power = Low Power = High BWOBSS Small Signal Bandwidth, 20mVpp, 3-dB BW, 100-pF Load Power = Low Power = High BWOBLS Large Signal Bandwidth, 1Vpp, 3-dB BW, 100-pF Load Power = Low Power = High Table 11-20. 3.3V AC Analog Output Buffer Specifications Parameter Description TROB Rising Settling Time to 0.1%, 1V Step, 100-pF Load Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100-pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100-pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100-pF Load Power = Low Power = High BWOBSS Small Signal Bandwidth, 20mVpp, 3dB BW, 100-pF Load Power = Low Power = High BWOBLS Large Signal Bandwidth, 1Vpp, 3dB BW, 100-pF Load Power = Low Power = High Min. Typ. Max. Unit s s s s Notes Min. Typ. Max. Unit s s s s Notes
- - - - 0.65 0.65 0.65 0.65 0.8 0.8 300 300
- - - - - - - - - - - -
2.5 2.5 2.2 2.2 - - - - - - - -
V/s V/s V/s V/s MHz MHz kHz kHz
- - - - 0.5 0.5 0.5 0.5 0.7 0.7 200 200
- - - - - - - - - - - -
3.8 3.8 2.6 2.6 - - - - - - - -
V/s V/s V/s V/s MHz MHz kHz kHz
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11.4.7 AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-21. AC Programming Specifications Parameter Description Min. Typ. Max. Unit Notes
TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3
11.4.8
Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK
AC I2C Specifications
1 1 40 40 0 - - - -
- - - - - 10 30 - -
20 20 - - 8 - - 45 50
ns ns ns ns MHz ms ms ns ns Vdd > 3.6 3.0 < Vdd < 3.6
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and 0C < TA < 70C, or 3.0V to 3.6V and 0C < TA < 70C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only.
Table 11-22. AC Characteristics of the I2C SDA and SCL Pins for Vdd Standard Mode Parameter Description Min. Max. Fast Mode Min. Max. Unit Notes
FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C TSUDATI2C TBUFI2C TSPI2C
SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Set-up Time Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter.
0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 -
100 - - - - - - - - -
0 0.6 1.3 0.6 0.6 0 100[11] 0.6 1.3 0
400 - - - - - - - - 50
kHz
s s s s s
THDDATI2C Data Hold Time TSUSTOI2C Set-up Time for STOP Condition
ns
s s
ns
Note: 11. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
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SDA TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Sr
P
S
Figure 11-4. Definition for Timing for Fast/Standard Mode on the I2C Bus
12.0 Packaging Information
This section illustrates the package specification for the CY7C64215 enCoRe III, along with the thermal impedance for the package.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/support/link.cfm?mr=poddim.
12.1 Packaging Dimensions
Figure 12-1. 56-Lead (8x8 mm) MLF Important Note For information on the preferred dimensions for mounting MLF packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
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51-85079-*C
Figure 12-2. 28-Lead Shrunk Small Outline Package
12.2 Thermal Impedance
Table 12-1. Thermal Impedance for the Package Package Typical JA *
56 MLF 28 SSOP * TJ = TA + POWER x JA
20 oC/W 96 oC/W
12.3 Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 12-2. Solder Reflow Peak Temperature Package Minimum Peak Temperature* Maximum Peak Temperature
56 MLF 28 SSOP
240C 240C
260C 260C
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 2205C with SnPb or 2455C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
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13.0 Ordering Information
.
Table 13-1. CY8C24794 PSoC Device Key Features and Ordering Information Package Ordering Code Flash Size SRAM (Bytes)
56 Pin MLF 28 Pin SSOP
CY7C64215-56LFXC CY7C64215-28PVXC
16K 16K
1K 1K
Microsoft and Windows are registered trademarks of Microsoft Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. enCoRe, PSoC, and Programmable System-on-Chip are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C64215
Document History Page
Description Title: CY7C64215, enCoReTM III Full Speed USB Controller Document Number: 38-08036 REV. ECN NO. Issue Date Orig. of Change Description of Change
** *A
131325 385256
See ECN See ECN
XGR BHA
New data sheet Changed from Advance Information to Preliminary. Added standard data sheet items. Changed Part number from CY7C642xx to CY7C64215.
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